A reconfigurable and scalable efficient architecture for AES
Date
2008
Authors
Li, Ke
University of Lethbridge. Faculty of Arts and Science
Journal Title
Journal ISSN
Volume Title
Publisher
Lethbridge, Alta. : University of Lethbridge, Deptartment of Mathematics and Computer Science, 2008
Abstract
A new 32-bit reconfigurable FPGA implementation of AES algorithm is presented in this
thesis. It employs a single round architecture to minimize the hardware cost. The combinational
logic implementation of S-Box ensures the suitability for non-Block RAMs
(BRAMs) FPGA devices. Fully composite field GF((24)2) based encryption and keyschedule
lead to the lower hardware complexity and convenience for the efficient subpipelining.
For the first time, a subpipelined on-the-fly keyschedule over composite field GF((24)2)
is applied for the all standard key sizes (128-, 192-, 256-bit). The proposed architecture
achieves a throughput of 805.82Mbits/s using 523 slices with a ratio throughput/slice of
1.54Mbps/Slice on Xilinx Virtex2 XC2V2000 ff896 device.
Description
ix, 77 leaves : ill. ; 29 cm.
Keywords
Data encryption (Computer science) , Dissertations, Academic